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Job Title:Verification Engineer
Position Type:Full time
Work experience:No requirements
Academic requirements:Master's degree
Release time:2015-07-15
1. Create the verification plan for full chip/block level with a high functional coverage by fully understanding the design specification.
2. Full chip/block level verification with constrained-random stimulus/coverage model using System verilog and UVM methodology.
3. Responsible for post simulation and debug.
4. Provide the test vectors for validation engineer.
5. Using firmware code(C/C++) to verify the ARM based SoC chip.
6. Help to build up the FGPA verification environment.
1. Good knowledge of UVM methodology. 2. Familiar with the EDA tools of design and verification. 3. Deep understanding of ASIC design and verification flow. 4. Good knowledge of SoC architecture. 5. Experience of C/C++ programming. 6. Must be a good team player and eager to success. 7. Strong communication, analytical skills. 8. BSEE/CS or MSEE/CS degree.
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